Real-Time Dynamic Digital Image Compression Using FPGAs
Real-Time Dynamic Digital Image Compression Technique Using Re-Configurable Hardware FPGAs
Image compression is the process of reducing the size of the image and data files. It is an important branch of the image processing technique that is still very active research field and attracts the industry. Image compression applications used with most of our communication systems exist these days. The recent expansion of image compression algorithms, multimedia based mobile phones, web applications, and wireless communication, together with the emerging new technologies has continued the need for more efficient ways to encode signals and images.
There are several issues regarded the current image compression technique in use today. First it mainly depends on the dedicated and rigid silicon hardware such as DSPs and ASICs. This causes inflexibility when implementing the transform algorithms. To overcome this Field Programmable Gate Arrays (FPGA), newer, more efficient system-on-chip configurable design devices that give system designers broad scale for implementing any old and new algorithm can be use. Secondly the available image compression software tools and hardware devices use only one Binary Discrete Cosine Transform (BinDCT) algorithm to code the complete image, although there are nine configurations of the algorithm. If the BinDCT coprocessor stay fixed on the same configuration, while the input image data stream frequency contents vary, then maximum coding gain and throughput cannot be achieved.
Figure 1: BinDCT Design using FPGAs Floorplanner
The main objective in this research will be constructing a generic system. This model should be able to run and switch dynamically between all nine BinDCT configurations within a reconfigurable Field Programmable Gate Array.The architecture of the forward and inverse BinDCT will typically consist of array of configurable blocks carry out BinDCT different logical functions as shown in Fig. 1.
Mahmoud Al-Ghreify.
